HD64570 Datasheet, PDF (181/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 5.8 TRB Read Operation in CPU Modes 2, 3
Data Byte Count in Receive Buffer*¹
Read Mode
Accessed Register*² 2 or More Bytes
1 Byte
None
Word read
TRBH
Data 0*³
Data 0*³
Undefined*⁴
TRBL
Data 1*³
Undefined*⁴ Undefined*⁴
Byte read
TRBH
Data 0*³
Data 0*³
Undefined*⁴
TRBL
Data 0*³
Data 0*³
Undefined*⁴
Notes: 1. Data byte count in the receive buffer is reflected by the CDE1 and CDE0 bits of current
status registers 1 and 0 (CTS1 and CTS0).
2. TRBH and TRBL are simultaneously accessed in word read mode, and either TRBH or
TRBL is accessed in byte read mode.
3. Data 0 and 1 are arranged in the order shown in figures 5.8 (a) and (b). The serial unit
sends data 0 and data 1 to the receive buffer in that order.
4. If undefined data is read, subsequent operation is not guaranteed. Undefined data is
not read in a built-in DMA transfer.
Data 0
Data 1
Data 0
(a) 2 Bytes of Data
in RX FIFO
(b) 1 Byte of Data
in RX FIFO
Figure 5.8 Data Arrangement in Receive Buffer
TRB write operation: Data is written to the transmit buffer at TRB write in the procedure as
listed in table 5.9 to table 5.11.
Rev. 0, 07/98, page 165 of 453