HD64570 Datasheet, PDF (340/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

In wait state insertion using the WAIT line, when the WAIT line is driven high, a wait state (T_W)
is inserted between states T₂ and T₃ (while the WAIT line maintains high). When the WAIT line
is driven low, the cycle advances to state T₃.
Figure 8.4 shows the wait state insertion timing using the WAIT line. The WAIT line level is
sampled at the falling edge of the system clock (CLK) pulse in state T₂ or T_W in CPU modes 1, 2,
and 3, and is sampled at the rising edge in CPU mode 0. Each time the high level of the WAIT
line is sampled at the falling edge (rising edge in CPU mode 0) of the CLK pulse in T_W state,
another T_W state is inserted.
An unlimited number of wait states can be inserted. (When more wait states are requested by the
register than by the WAIT line, the T_W states requested by the register are inserted.)
Note that, for driving the WAIT line signal high, the set-up time and hold time for the falling edge
(rising edge in CPU mode 0) of the CLK pulse must be accounted for by synchronizing it to the
rising edge (falling edge in CPU mode 0) of the CLK pulse. If not, correct operation is not
guaranteed.
System clock (CLK)
(CPU modes 1, 2, and 3)
T₁
T₂
T_W T_W
T₃
T₁
System clock (CLK)
(CPU mode 0)
WAIT
Sampling Sampling Sampling
Figure 8.4 Wait State Insertion Timing Using the WAIT Line
8.3.2 Wait State Insertion Using the Register
Wait states can be inserted in a DMA bus cycle, using wait control registers WCRL, WCRM, and
WCRH, eliminating the need for an external circuit. The optimum number of wait states can be
inserted into a DMA bus cycle by software, according to the memory used. Figure 1.28 shows an
example of dividing the memory space for interfacing three different types of memory. In this
example, any desired number of wait states can be independently specified for each of the three
types of memory. (When more wait states are requested using the WAIT line than those using the
register, as many T_W states as requested by the WAIT line are inserted.) Physical address
boundaries for dividing the memory space into three memory areas are specified by the physical
address boundary registers 0 and 1 (PABR0 and PABR1). For details, see section 8.2.1, Physical
Rev. 0, 07/98, page 324 of 453