HD64570 Datasheet, PDF (19/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 1.1 Major Functions of the SCA (cont)
Item
DMAC
(direct memory
access controller)
Specification
Number of channels 4
Transfer modes
DMA transfer between memory and on-chip MSCI:
1. Single block transfer (asynchronous, byte-synchronous, bit-
synchronous modes)
2. Chained-block transfer (bit-synchronous mode)
Timers
Minimum transfer 3 clocks
cycle
Number of channels 4
Counter length
16 bits
Interrupt controller
Acknowledge cycle Programmable:
1. Nonacknowledge cycle
2. Single acknowledge cycle
3. Double acknowledge cycle
Vector output mode Programmable:
1. Fixed vector output mode
2. Modified vector output mode
Wait state controller
On-chip (register programmable, or external line control)
Bus arbiter
On-chip (can be daisy-chained)
Low-power mode
System stop mode supported
Maximum system clock rate
10 MHz or 16.7 MHz
Signal level
TTL-compatible
Supply voltage
+5 V ± 10% (−20 to 75°C) for 10-MHz chip
+5 V ± 5% (0 to 70°C) for 16.7-MHz chip
+5 V ± 10% (−40 to 85°C) for 8-MHz chip*
Process
CMOS
Package
CP-84: 84-pin QFJ (PLCC) (quad flat j-leaded package (plastic
leaded chip carrier))
FP-88: 88-pin QFP (quad flat package)
Product lineup
Type
Product
Number
Maximum Operating Voltage
Operating
Frequency
Package
SCA
HD64570CP 10 MHz +5 V ± 10% (−20 to 75°C) CP-84 (84-pin QFJ
(PLCC))
HD64570F
FP-88 (88-pin QFP)
High Speed HD64570CP1616.7 MHz +5 V ±5%
SCA
(0 to 70°C)
CP-84 (84-pin QFJ
(PLCC))
HD64570F16
FP-88 (88-pin QFP)
WTR SCA HD64570CP8I 8 MHz
+5 V ±10%
(−40 to 85°C)
CP-84 (84-pin QFJ
(PLCC))*
HD64570F8I
FP-88 (88-pin QFP)*
Rev. 0, 07/98, page 3 of 453