HD64570 Datasheet, PDF (225/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.4.3 Receive Clock Sources
The receive clock sources are shown in figures 5.31 (a), (b), and (c). When the RXC signal is not
used as a clock source, the RXC line functions as the receive clock output line.
In asynchronous mode, the actual bit rate is determined by the clock mode (1/1, 1/16, 1/32, or
1/64). In byte or bit synchronous mode, 1/1 clock mode is automatically selected. For details, see
section 5.2.2, MSCI Mode Register 1 (MD1).
CLK
Receive
baud rate
generator
f _{BRG =}
f_CLK
TMC
÷ 2^RXBR
(TMC: 1 to 256, RXBR: 0 to 9)
f _BR
RXC line
Receive clock
(1/1, 1/16, 1/32 or
1/64 clock mode)
(Receive BRG output used as receive clock)
f_CLK : System clock (CLK) frequency
(a) Receive BRG Output or RXC Line Input Used as Receive Clock
RXD line
Receive data
f _{BRG =}
f_CLK
TMC
÷ 2^RXBR
(TMC: 1 to 256, RXBR: 0 to 9)
Receive
CLK
baud rate
generator ^f _BR
RXC line
ADPLL
operating
clock
Clock extracted from the receive data
ADPLL
(Sampling rate:
operating clock
× 8,× 16×, 32)
Receive clock
(1/1 clock mode)
(Receive BRG output used as the ADPLL operating clock)
f_CLK : System clock (CLK) frequency
(b) Clock Extracted by ADPLL Used as Receive Clock
Figure 5.31 Receive Clock Sources
Rev. 0, 07/98, page 209 of 453