HD64570 Datasheet, PDF (336/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Physical address boundary
register 1 (PABR1)
Physical address boundary
register 0 (PABR0)
FFFFFFH
PAH area
PAM area
000000H
PAL area
Physical address space
(d) Physical Address Partitioned into PAH, PAM and PAL
Figure 8.2 Boundary Address Setting Examples (cont)
Precautions: Normal operation is not guaranteed if the boundary specified by PABR0 is higher
than that specified by PABR1. An example of this type is shown in figure 8.3. (Setting PABR0 to
00H and PABR1 to a value other than 00H may also disable normal operation.)
Physical address boundary
register 0 (PABR0)
FFFFFFH
Physical address boundary
register 1 (PABR1)
000000H
Physical address space
Figure 8.3 Incorrect Boundary Address Setting Example
8.2.2 Wait Control Registers L, M, H (WCRL, WCRM, WCRH)
Wait control registers WCRL, WCRM, and WCRH specify the number of wait states to be
inserted each physical address areas and PAL, PAM, PAH.
Wait Control Register L (WCRL): Specifies the number of wait states to be inserted in a
memory cycle when the PAL area is accessed.
Rev. 0, 07/98, page 320 of 453