HD64570 Datasheet, PDF (31/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

1.6.6 Timer Registers
Address
CPU Modes 0 & 1
CPU Modes 2 & 3
Initial Value at
Hardware Reset
Read/
Write
Register
Name
Chan- Chan- Chan- Chan- Chan- Chan- Chan- Chan-
Symbol nel 0 nel 1 nel 2 nel 3 nel 0 nel 1 nel 2 nel 3
MSB
LSB
Timer up-
counter
TCNTL 60H 68H 70H 78H 61H 69H 71H 79H 0 0 0 0 0 0 0 0 R/W
TCNTH 61H 69H 71H 79H 60H 68H 70H 78H 0 0 0 0 0 0 0 0 R/W
Timer
constant
register
TCONRL 62H 6AH 72H 7AH 63H 6BH 73H 7BH 1 1 1 1 1 1 1 1* W
TCONRH 63H 6BH 73H 7BH 62H 6AH 72H 7AH 1 1 1 1 1 1 1 1* W
Timer
TCSR 64H 6CH 74H 7CH 65H 6DH 75H 7DH 0 0 0 0 0 0 0 0 R/W
control/status
register
Timer expand TEPR 65H 6DH 75H 7DH 64H 6CH 74H 7CH 0 0 0 0 0 0 0 0 R/W
prescale
register
Note: The timer constant register is a write-only register that always reads as 0000H.
1.6.7 Wait Controller Registers
CPU Modes CPU Modes ^{Initial Value at Hardware Reset} Read/
0&1
2&3
Write
Register Name Symbol
MSB
LSB
Physical address PABR0 02H
03H
0 0 0 0 0 0 0 0 R/W
boundary register 0
Physical address PABR1 03H
02H
0 0 0 0 0 0 0 0 R/W
boundary register 1
Wait control
WCRL 04H
05H
0 0 0 0 0 1 1 1 R/W
register L
Wait control
WCRM 05H
04H
0 0 0 0 0 1 1 1 R/W
register M
Wait control
WCRH 06H
07H
0 0 0 0 0 1 1 1 R/W
register H
Rev. 0, 07/98, page 15 of 453