HD64570 Datasheet, PDF (371/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

10.2.3 AC Characteristics
Table 10.16 CPU Mode 0 Slave Mode Bus Timing
(V_CC = 5 V ± 5%, V_SS = 0 V, Ta = 0 to +70°C unless otherwise specified)
Item
Symbol Min Typ
CS set-up time
CS hold time 1
CS hold time 2
t _CSS
t _CSH1
t _CSH2
15

20

0

Address set-up time
t _ADS
15

Address hold time
RD active set-up time
RD inactive set-up time
RD inactive hold time
RD active hold time
WR active set-up time
WR inactive set-up time
WR inactive hold time
WR active hold time
t _ADH
t _RDS1
t _RDS2
t _RDH1
t _RDH2
t _WRS1
t _WRS2
t _WRH1
t _WRH2
0

15

10

10

0

15

10

10

0

WAIT active delay time
t _WTD1


WAIT inactive delay time
t _WTD2


Read data active delay time
t _DBD1


Read data hold time
t _DBD2
10

Read data floating delay time
t _DBZ


Write data set-up time
t _DBS
20

Write data hold time
t _DBH
20

Note: The CLK timing is the same in this mode and DMA mode.
Max













50
50
60

60


Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing
Figure 10.1
Rev. 0, 07/98, page 355 of 453