HD64570 Datasheet, PDF (91/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

• Read cycle
When R/W is high, if HDS or LDS is low (active) at the rising clock edge between the T₁ and
T₂ states, the SCA outputs the contents of the register specified by the address on the data bus
on the falling clock edge in the T₃ state. HDS or LDS must remain low until the beginning of
the T₅ state. When HDS or LDS goes high (inactive), the cycle ends: the SCA then drives the
WAIT output active high and lets the data bus float. The read cycle can be extended by
delaying the high transition of HDS or LDS.
• Write cycle
When R/W is low, if HDS or LDS is low (active) at the rising clock edge between the T₂ and
T₃ states, the SCA latches the data on the data bus on the falling clock edge in the T₃ state, and
stores the data in the register specified by the address. HDS or LDS must remain low until the
falling clock edge in the T₅ state. When HDS or LDS goes high (inactive), the cycle ends: the
SCA drives the WAIT output active high.
CLK
A₁ to A ₇
AS
T₁ T₂
T₃
T₄
T₅
T₁
T₂
T₃
T₄
T₅
Register address
Register address
CS
HDS, LDS
R/W
WAIT
D₀ to D₁₅
(Out)
D₀ to D₁₅
(In)
Output data
Read cycle SCA ^→MPU
Input data
Data latch point
Write cycle MPU ^→SCA
Note: State numbers do not match MPU state numbers.
Figure 3.12 Slave Mode Bus Timing Sequence in CPU Mode 3
Rev. 0, 07/98, page 75 of 453