HD64570 Datasheet, PDF (259/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Chained-Block Transfer Mode: In chained-block transfer mode, the 8-bit subregister composed
of bit 23–bit 16 serves as the chain pointer base (CPB) for specifying the high-order eight bits of
the 24-bit descriptor address. When the high-order eight bits are specified, the 64-Kbytes memory
space is used as the descriptor area.
This register must be set in DMA initial state.
After reset, the value of these registers is undefined.
• Channels: 0, 2
B
H
L
23
16 15
87
0
Single-block transfer
mode
Chained-block
transfer mode
Not used
CPB
Not used
Not used
Not used
Not used
• Channels: 1, 3
B
H
L
23
16 15
87
0
Single-block transfer
mode
Chained-block
transfer mode
SARB
CPB
SARH
Not used
SARL
Not used
Note: In chained-block transfer mode, bit 15–bit 0 are used for internal operations.
Nothing, therefore, must be written to them.
Figure 6.2 Source Address Register/Chain Pointer Base
Rev. 0, 07/98, page 243 of 453