HD64570 Datasheet, PDF (341/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Address Boundary Registers 0, 1 (PABR0, PABR1). The number of wait states to be inserted in
each memory area is specified by wait control registers WCRL, WCRM, and WCRH. For details,
see section 8.2.2, Wait Control Registers L, M, H (WCRL, WCRM, WCRH).
8.4 Operation in System Stop Mode
When the wait controller stops in system stop mode, the current register contents are retained.
8.5 Reset Operation
At reset, the wait controller stops and its registers are initialized as follows:
• The wait control registers (WCRL, WCRM, and WCRH) are initialized so that the maximum
number of wait states are inserted.
• The physical address boundary registers (PABR0 and PABR1) are initialized to 00H. This
results in the physical address space consisting of only PAL. Accordingly, the number of wait
states specified by WCRL is inserted in a DMA cycle.
8.6 Precautions
If wait state insertion is simultaneously requested by the register and WAIT line, the number of
wait states specified by the register are inserted. If the WAIT line later requests more wait states
than the register, the additional wait states are then inserted.
Rev. 0, 07/98, page 325 of 453