HD64570 Datasheet, PDF (45/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Memory
DMAC
SCA
MSCI
DMA Request
TXRDY active
If the number of bytes of data in TX
FIFO has dropped to the number set in
MSCI TX ready control register 0 (TRC0)
or less, and has not subsequently risen
to the number set in MSCI TX ready
control register 1 (TRC1) + 1 or greater
Get bus
Access memory
1. Put address on bus (A₀to A₂₃)
2. AS active
3. RD active
Send data
1. Decode address
2. Put data on bus
3. WAIT inactive
MSCI response
1. Read data
2. If the number of bytes of data in
TX FIFO after this transfer is equal to
or greater than the number set in MSCI
TX ready control register 1 (TRC1) + 1,
negate TXRDY (to inactivate the DMA
request)
End of transfer
AS and RD inactive
End of cycle
WAIT active
Relinquish bus
Or start next cycle
Figure 1.17 Transmit DMA Operation (CPU mode 1)
Rev. 0, 07/98, page 29 of 453