HD64570 Datasheet, PDF (291/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

transfer is completed within one frame, after which the DMAC enters initial state. Here, the DE
bit of DSR is automatically cleared. When the DE bit is set to 1 again, the DMAC restarts
operation.
Table 6.4 Control Registers Used in Memory-to-MSCI Chained-Block Transfer Mode
(transmission)
Register Chain Pointer Base
Name
(CPB)
Error Descriptor
Address Register (EDA)
Current Descriptor
Address Register (CDA)
Number of 8
bits
16
16
Function
Specifies the high-order
Specifies the low-order
8 bits of the 24-bit descriptor 16-bits of the start address
start address.
of the descriptor corre-
sponding to the buffer
following the last transmit
buffer.
Specifies the low-order
of the descriptor
corresponding to the first
transmit buffer.
This address is updated
by the DMAC during
buffer chaining.
Role in —
—
After the DMAC starts,
DMAC
operation
it loads the low-order
16 bits of the start
address of the descriptor
corresponding to the
buffer being transferred
into the MSCI.
Transfer ends when a transfer request is issued while
the EDA and CDA match. An interrupt is generated, if
enabled.
Register Under MPU control.
update
Under MPU control.
When the current buffer
read is completed, the
next descriptor start
address is automatically
loaded into this register.
Register
updated
by the
MPU
Initialized before
transmission.
Loaded with the start
The start address of the
address of the descriptor descriptor indicating the
indicating the buffer following first buffer containing
the last buffer containing transmit data is loaded
transmit data. To add
before transmission
transmit data during a
starts.
transmission, load the start
address of the descriptor
indicating the next buffer to
be written.
Rev. 0, 07/98, page 275 of 453