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| HD64570 Datasheet, PDF (77/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor | |||
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System stop mode is released when the RESET signal becomes active for six clock cycles or
more, placing the SCA in reset mode.
CLK
BHE
A0 to A7
CS
T1
T2
T3
T4
WR
D0 to D15
Normal operating mode
System stop mode
CLK
A0 to A7
(a) CPU mode 0
T1
T2
T3
T4
T5
CS
WR
D0 to D7
Normal operating mode
System stop mode
(b) CPU mode 1
Figure 3.3 Timing of Transition to System Stop Mode
Rev. 0, 07/98, page 61 of 453
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