HD64570 Datasheet, PDF (191/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

The transmit and receive bit rates can be independently selected from the input frequency ratios
1/1, 1/16, 1/32, or 1/64 by using the BRATE1−BRATE0 bits of MD1 (figure 5.11). (The selected
bit rate is used for both transmission and reception.) Since data is sampled at the rising edge of the
clock pulse, bit-by-bit synchronization is necessary when the 1/1 clock mode is selected (figure
5.12).
MD register 1 (BRATE1, 0)
1/1, 1/16, 1/32, 1/64)
External line
(TXC line)
Baud rate
generator
External line
(RXC line)
Divider
Divider
Transmitter
Receiver
Figure 5.11 Bit Rate Selection
Receive data
Receive clock
Sampling at the rising edge of the clock pulse
Figure 5.12 Data Sampling Timing (1/1 clock mode)
The external clock or internal baud rate generator output can be program-selected as the
input/output clock. The ADPLL clock extraction function is not available in asynchronous mode.
The clock can be specified with the RX clock source register (RXS) and TX clock source register
(TXS). For details, see section 5.2.5, MSCI RX Clock Source Register (RXS), and section 5.2.6,
MSCI TX Clock Source Register (TXS).
For details on the internal baud rate generator, see section 5.6, Baud Rate Generator.
Rev. 0, 07/98, page 175 of 453