HD64570 Datasheet, PDF (301/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

6.4.4 MSCI-to-Memory Chained-Block Transfer Mode
Operation: In MSCI-to-memory chained-block transfer mode, frame-bounded data is DMA-
transferred from the MSCI receiver (in bit synchronous mode) to a system memory buffer.
Transfer requests are initiated by the MSCI internal signal. Note that chained-block transfer mode
is not available with the MSCI operated in asynchronous or byte synchronous mode.
MSCI-to-memory transfer employs DMAC channels 0 and 2. For this transfer mode, follow the
steps below starting with the DMA in its initial state. (Steps 1 to 6 may be completed in any
order.)
1. Specify chained-block transfer mode with the DMA mode register (DMR).
2. Load the high-order eight bits of the 24-bit descriptor address into the chain pointer base
(CPB). Since the CPB value is fixed during operation, descriptors can be assigned to any
consecutive 64-Kbyte area in system memory.
3. Load the low-order 16 bits of the start address of the descriptor, which indicates the buffer
next to the last receive buffer, into the error descriptor address register (EDA).
4. Load the low-order 16 bits of the start address of the descriptor, which indicates the first
receive buffer, into the current descriptor address register (CDA).
5. Load the buffer length in byte units into the receive buffer length (BFL). (This value is
shared by all buffers.)
6. Initialize the chain pointer (CP) and buffer pointer (BP) in each descriptor.
7. After steps 1 to 6, set the DE bit of the DMA status register (DSR) to 1 to start a DMA
operation.
MSCI-to-memory chained-block transfer mode is shown in figure 6.18.
Rev. 0, 07/98, page 285 of 453