HD64570 Datasheet, PDF (405/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CLK
t_BRQD
BUSREQ
t_RAKS
BUSACK
BEO
BUSY
(Out)
BUSY
(In)
t_BSYS
t_BEOD
t_BSYD
Note: This figure merely defines the symbols for AC timing; see figure 3.6 for specific
bus arbitration timing.
Figure 10.13 CPU Mode 1, 2, 3 Bus Arbitration Timing
TXC
(Input)
TXD
(Output)
t _TCf
t _TCLW
t _TDD1
t _TCr
t_TCHW
t_TCYC
t _TDD1*1
Note ^*1: There is no transition of the TXD at this point in NRZ mode.
Figure 10.14 Transmit Timing (TXC input)
Rev. 0, 07/98, page 389 of 453