HD64570 Datasheet, PDF (179/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.21 MSCI TX/RX Buffer Register (TRB: TRBH, TRBL)
The TX/RX buffer register (TRB: TRBH, TRBL), located at the top of the 32-stage
transmit/receive buffer (TX/RX buffer), interfaces with the internal data bus. Although the TX
and RX buffers are physically different, this register is used for both reading receive data from the
RX register and writing transmit data to the TX buffer.
7
6
5
4
3
2
1
0
TRBH
Async
Byte sync
TRB15 TRB14 TRB13 TRB12 TRB11 TRB10 TRB9 TRB8
(TRBH7()TRBH6()TRBH5()TRBH4()TRBH3()TRBH2()TRBH1()TRBH0
Bit sync HDLC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
X
X
X
X
X
Value written to, or read from, the transmit/receive buffer
X: Undefined
7
6
5
4
3
2
1
0
Async
TRBL ^{Byte sync}
TRB7 TRB6 TRB5 TRB4 TRB3 TRB2 TRB1 TRB0
(TRBL7)(TRBL6)(TRBL5)(TRBL4)(TRBL3)(TRBL2)(TRBL1)(TRBL0
Bit sync HDLC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
X
X
X
X
X
Value written to, or read from, the transmit/receive buffer
X: Undefined
Rev. 0, 07/98, page 163 of 453