HD64570 Datasheet, PDF (90/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

• Read cycle
When R/W is high, if HDS or LDS is low (active) at the rising clock edge between the T₂ and
T₃ states, the SCA outputs the contents of the register specified by the address on the data bus
on the falling clock edge in the T₄ state. HDS or LDS must remain low until the beginning of
the T₅ state. When HDS or LDS goes high (inactive), the cycle ends: the SCA then drives the
WAIT output active high and lets the data bus float. The read cycle can be extended by
delaying the high transition of HDS or LDS.
• Write cycle
When R/W is low, if HDS or LDS is low (active) at the falling clock edge in the T₃ state, the
SCA latches the data on the data bus on the falling clock edge in the T₄ state, and stores the
data in the register specified by the address. HDS or LDS must remain low until the falling
clock edge in the T₆ state. When HDS or LDS goes high (inactive), the cycle ends: the SCA
then drives the WAIT output active high.
CLK
T₁ T₂
T₃
T₄
T₅
T₁
T₂
T₃
T₄
T₅
T₆
A₁ to A ₇
Register address
Register address
AS
CS
HDS, LDS
R/W
WAIT
D₀ to D₁₅
(Out)
D₀ to D₁₅
(In)
Read cycle SCA ^→MPU
Output data
Input data
Data latch point
Write cycle MPU ^→SCA
Note: State numbers do not match MPU state numbers.
Figure 3.11 Slave Mode Bus Timing Sequence in CPU Mode 2
CPU Mode 3: The SCA latches the address on lines A₁ to A₇ when CS and AS are both driven
active low. CS and AS must remain low throughout the bus cycle. After the bus cycle ends, they
must go high (inactive). Figure 3.12 shows the slave mode bus timing sequence in CPU mode 3.
Rev. 0, 07/98, page 74 of 453