HD64570 Datasheet, PDF (307/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.8 MSCI-to-Memory Chained-Block Multi-Frame Transfer Mode (normal
reception operation)
DMAC
Step Operation
MPU
CDA EDA DE Bit
Operation Value Value Value Note
1
—
A₂ ‡ CDA A₂
A₁
1
A₁ ‡ EDA
1 ‡ DE bit
Specifies the buffer where
receive data is to be written using
CDA and EDA (figure 6.20)
2
Writes data to —
buffer 2
A₂
A₁
1
3
A₃ ‡ CDA
A2 ‡ EDA A₃
A₂
1
Writes A₂ to EDA to reserve the
maximum buffer size
4
Writes data to —
buffer 3
A₃
A₂
1
5
A₀ ‡ CDA
—
→
A₀
A₂
1
8
Writes data to —
buffer 1
A₁
A₂
1
9
A₂ ‡ CDA
—
A₂
A₂
1
If another write request is issued in
this state, the DMAC generates a
DMIA interrupt (figure 6.20)
A_n: Start address of each descriptor
CDA: Current descriptor address register
EDA: Error descriptor address register
DE bit: Bit 1 of the DMA status register (DSR)
Rev. 0, 07/98, page 291 of 453