HD64570 Datasheet, PDF (139/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.6 MSCI TX Clock Source Register (TXS)
The TX clock source register (TXS) specifies the transmit clock source and the baud rate of the
baud rate generator (BRG) in the transmitter. For details on the baud rate generator, see section
5.6, Baud Rate Generator.
This register is reset under either of the following conditions:
• Hardware reset
• Channel reset command
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
7
6
5
4
3
2
1
0
—*1 _{TXCS2 TXCS1 TXCS0 TXBR3 TXBR2 TXBR1 TXBR0}
— R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
Transmit clock source
000: TXC line input
100: Internal baud rate generator (BRG) output
110: Receive clock
Others: Reserved ^*2
Transmitter baud rate
• Clock division ratio
0000: 1/1
0001: 1/2
0010: 1/4
0011: 1/8
0100: 1/16
0101: 1/32
0110: 1/64
0111: 1/128
1000: 1/256
1001: 1/512
*2
Others: Reserved
Notes: 1. Reserved. This bit always reads 0 and must be set to 0.
2. Reserved. When these settings are selected, normal operation is not guaranteed.
Rev. 0, 07/98, page 123 of 453