HD64570 Datasheet, PDF (272/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

6.2.11 DMA Command Register (DCR)
The DMA command register (DCR), provided for each of channels 0, 1, 2, and 3, issues a
software abort or a frame end interrupt counter clear command to the DMAC. This register
always reads 00H.
7
6
5
4
3
2
1
0
Single-block
transfer mode _{—*1 —*1 —*1 —*1 —*1 —*1 DCMD1DCMD0}
Chained-block
transfer mode
Read/Write
Initial value
—— ————W W
—— ——————
Command specification^*2
01: Software abort
10: Frame end interrupt
counter cleared
Others: Reserved
Notes: 1. Reserved. These bits always read 0 and must be set to 0.
2. These commands must not be issued when the corresponding DMAC
channel is enabled (DE = 1). No values other than those shown here
(01H and 02H) must be written to these bits.
Bits 7–2: Reserved. These bits always read 0 and can be set to 0.
Bits 1–0 (DCMD1–DCMD0: Command): The function of these bits in either single-block
transfer mode or chained-block transfer mode is described below.
DCDM1, DCDM0 = 0, 1: Issues a software abort command; initializes the corresponding DMAC
channel (figure 6.7). All DMAC registers retain their previous values.
DCDM1, DCDM0 = 1, 0: Issues a frame end interrupt clear command; clears the frame end
interrupt counter (FCT) of the corresponding DMAC channel to 0000
and the EOM bit of the DMA status register (DSR) to 0.
Other settings: Inhibited
If the DMAC is disabled by software (the DE bit of DSR cleared) for a new operation, the DMAC
must be initialized by a software abort command. This is necessary because the DMAC retains its
internal state even after being disabled. However, if the DMAC was disabled when the transfer
end conditions were satisfied, a software abort command is not necessary.
Rev. 0, 07/98, page 256 of 453