HD64570 Datasheet, PDF (433/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Address
Register
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
MSCI (Channel 1)
MSCI Status Register 2
44H 45H
Channel 1: ST2 Channel 1
Async
Byte sync
7
6
5
4
3
2
1
0
— PMP PE FRME OVRN — — —
———
CRCE
Bit sync HDLC EOM SHRT ABT RBIT
Read/Write R/W R/W R/W R/W R/W R/W — —
Initial value
0
0
0
0
0
0
0
0
SCI Status Register 3
45H 44H
Channel 1: ST3 Channel 1
Receive end of message
• Bit synchronous mode
0: Receive frame end
not detected
1: Receive frame end
detected
Framning error
• Asynchronous mode
0: No framing error
detected
1: Framing error
detected
Parity/MP bit
Residual bit frame
• Asynchronous mode
• Bit synchronous
0: Parity/MP bit = 0
mode
1: Parity/MP bit = 1
0: Normal end of
Short frame
• Bit synchronous mode
0: Normal end of frame
frame
1: Residual bit frame
detected
1: Short frame detected
Overrun error
0: No overrun error detected
Parity error
1: Overrun error detected
• Asynchronous mode
0: No parity error detected
CRC error
1: Parity error detected
• Byte/Bit synchronous mode
Abort end frame
• Bit synchronous mode
0: No CRC error detected
1: CRC error detected
0: Normal end of frame
1: Frame with abort end detected
7
Async
—
Byte sync
Bit sync HDLC
Read/Write
—
Initial value
0
6
5
4
3
2
1
0
— — — CTS DCD TXENBLRXENBL
SRCH
SLOOP
—
R
R
R
R
R
R
0
0
0
X
X
0
0
Sending on loop
• Bit synchronous mode
0: Transmits no MSCI data
1: Transmits MSCI data
CTS input line status
0: CTS low level
1: CTS high level
TX enable
0: Disable
1: Enable
RX enable
0: Disable
Search mode
• Byte/Bit synchronous mode
1: Enable
0: ADPLL normal mode
1: ADPLL search mode
DCD input line status
0: DCD low level
1: DCD high level
Rev. 0, 07/98, page 417 of 453