HD64570 Datasheet, PDF (133/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

CNCT1, CNCT0 = 0, 0: Specifies the full duplex communications mode (normal operation)
CNCT1, CNCT0 = 0, 1: Specifies the auto-echo mode. In this mode, input data via the RXD
line is directly output to the TXD line. (If specified, the data is first processed by the ADPLL
to suppress noise and extract the clock signal, and the resulting data is output on the TXD line.)
This mode enables data reception, but disables data transmission. If the MSCI TX clock
source register (TXS) designates TXC as an output line, the receive clock selected by the
MSCI RX clock source register (RXS) is output on the TXC line. If TXC is designated as an
input line, the TXC input does not affect operations.
CNCT1, CNCT0 = 1, 0: Reserved.
CNCT1, CNCT0 = 1, 1: Specifies the local loop-back mode. In this mode, the transmit shift
register output is internally connected to the receive shift register input for the receive shift
register to directly receive the transmit data without passing through the ADPLL. Here, the
receive clock selected by the MSCI RX clock source register (RXS) is used as both the
transmit clock and receive clock.
Independently of the above operation, data input on the RXD line is output again on the TXD
line. (If specified, the data is first processed by the ADPLL to suppress noise and extract the
clock signal, and the resulting data is output on the TXD line.)
In addition, if the TXS register designates TXC as an output line, the receive clock selected by
the RXS register is output on the TXC line. If TXC is designated as an input line, the TXC
input does not affect operations.
Note that if the ADPLL output is selected as the receive clock, the clock signal extracted from
the RXD input is supplied to both the transmitter and receiver.
5.2.4 MSCI Control Register (CTL)
The control register (CTL) specifies the transmit operation in underrun state, an output pattern for
idle state in byte or bit synchronous mode, break send in asynchronous mode, SYN character
transfer from the data field to the receive buffer, and the RTS line output level.
This register is reset under either of the following conditions:
• Hardware reset
• Channel reset command
The BRK bit (bit 3) is also cleared by a TX reset command.
Rev. 0, 07/98, page 117 of 453