HD64570 Datasheet, PDF (146/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 5.2 Receive Commands (cont)
Command Name
(Set Value)
Forcing RX CRC
calculation (18H)
Function
Forcibly starts CRC calculation of the 8-bit data in the RX delay register.
In byte synchronous mode, this command must be issued after the second
byte of the CRC code enters the receive buffer. This allows CRC
calculation to be completed even when the receive clock is halted after
CRC code reception.
CRC error status is activated 15 system clock cycles after this command is
issued and remains valid until the next data enters the receive buffer.
Table 5.3 Other Commands
Command Name
(Set Value)
Channel reset (21H)
Enter search mode
(31H)
No operation (00H)
Function
Initializes all MSCI registers, sets the transmitter and receiver to disable
state, and clears the transmit/receive buffer.
Sets the ADPLL to search mode. For FM code transmission,
synchronization between the extracted receive clock and receive data can
be established by a single transition point. This command also sets the
SRCH bit of status register 3 (ST3) to 1.
For details, see section 5.5, ADPLL.
Allows the transmitter and receiver to continue the current operation.
Rev. 0, 07/98, page 130 of 453