HD64570 Datasheet, PDF (231/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Receive data
(For receive data)
Noise
suppressor
Data
delay unit
ADPLL
operating
clock
Clock line 1
Receive BRG
output
External clock
Clock line 2
Multiplexor
(RXC line input)
Clock
extractor
Noise-
suppressed
receive data
Extracted
clock
Noise
suppressor
(For receive clock)
Receive data
ADPLL operating
clock
Receive clock
Figure 5.33 Data and Clock Signal Flow for Clock Extraction from Receive Data
The specific operation of the ADPLL are as follows:
• The receive data noise suppressor receives receive data and suppresses noise.
• The noise suppressor outputs the noise-suppressed receive data to the clock extractor and data
delay unit.
• The data delay unit outputs the noise-suppressed receive data to the receiver, synchronizing the
data with the extracted clock.
• The clock extractor extracts clock components from the noise-suppressed receive data and
outputs the resulting clock signal.
• The ADPLL operating clock (the receive baud rate generator output or external clock) passes
through the multiplexor to the clock extractor, receive data noise suppressor, and data delay
unit.
The ADPLL outputs the noise-suppressed receive data and extracted clock, synchronizing their
phases using the ADPLL phase compensation function. Phase compensation for the NRZ- and
FM0-code receive data is shown in figures 5.34 and 5.35.
In the figures, the ADPLL outputs the noise-suppressed receive data from the noise suppressor to
the data delay unit and clock extractor. The clock extractor samples the noise-suppressed receive
data at the rising edge of the ADPLL operating clock pulse, and performs clock extraction.
The ADPLL compares the phases of the receive data and extracted clock at level transition points
(T_S, T_S-1, T_S-2) in the receive data output from the data delay unit. If the two phases are skewed,
the extracted clock cycle is lengthened or shortened by one ADPLL operating clock cycle. In the
examples shown in figures 5.38 and 5.39 (operating mode = × 8), this synchronization can be
Rev. 0, 07/98, page 215 of 453