HD64570 Datasheet, PDF (412/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Appendix B Registers
Address
Register
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
System
Low Power Register (LPR) 00H 01H
Not used
01H 00H
Bit name
Read/Write
Initial value
7
6
5
4
3
2
1
0
— — ——
——
— IOSTP
— — — — — — — R/W
0
0
0
0
0
0
0
0
Wait Control
Physical Address
Boundary Registers 0
(PABR0)
02H
03H
Bit name
Read/Write
Initial value
I/O stop
0: No transition to system stop mode
1: Transition to system stop mode
7
6
5
4
3
2
1
0
PB07 PB06 PB05 PB04 PB03 PB02 PB01 PB00
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
Physical Address
Boundary Registers 1
(PABR1)
03H
02H
Bit name
Read/Write
Initial value
PAL/PAM boundary address (high-order 8 bits)
7
6
5
4
3
2
1
0
PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
Wait Control Registers L
(WCRL)
04H
05H
Bit name
Read/Write
Initial value
PAM/PAH boundary address (high-order 8 bits)
7
6
5
4
3
2
1
0
— — — — — PALW2PALW1 PALW0
— — — — — R/W R/W R/W
0
0
0
0
0
1
1
1
PAL area wait
Rev. 0, 07/98, page 396 of 453