HD64570 Datasheet, PDF (64/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 2.6 Bus Interface Lines (cont)
Pin Number
Symbol CP-84
BHE/HDS*¹ 6
FP-88
17
CS
82
9
*1: Not connected
Input/
Output
Description
Input/ CPU mode 0
output
Bus high enable: High-order byte access signal.
Master mode Output.
Slave mode Input.
Reset mode Input.
System stop Input.
mode
CPU mode 1
*¹
Always high. Leave
unconnected, or pull up to V_CC.
CPU modes 2, 3
Higher data strobe: Strobe timing for the high-
order data bits.
Master mode Output.
Slave mode Input.
Reset mode Input.
System stop Input.
mode
Input/ Chip select: Selects the SCA.
output
CPU modes 0−3
Master mode Input, but ignored by the SCA.
Slave mode
Indicates access by a host
MPU. An internal register
read/write cycle starts when
this line is driven active low.
Reset mode Input, but ignored by the SCA.
System stop Input, but ignored by the SCA.
mode
Rev. 0, 07/98, page 48 of 453