HD64570 Datasheet, PDF (193/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Initialization by reset
"TX disable"
issued after transmission
"TX disable" not issued
and data remaining in
transmit buffer
Break transmission
One-bit cycle
specified in
mark transmit
any state
state
Break reset
specified
"TX disable"
not issued
TX disable
state
"TX enable" issued Idle state
"TX disable" issued
and no data _{Break transmit}
remaining in
state
transmit buffer
after transmission
"TX reset" or
"channel reset"
issued in any
state
Start bit
transmit state
No data remaining in transmit
Data written to transmit buffer buffer after transmission
No parity/MP
detected after
After
Character
transmit state
transmission
Stop bit
transmit state
transmission
Parity/MP detected
after transmission
After transmission
Parity/MP bit
transmit state
Data remaining
in transmit buffer
after transmission
Note: Command names are enclosed in double quotation marks ("").
Figure 5.13 State Transition Diagram for Transmission in Asynchronous Mode
Transmission operation starts when a transmit character is written to the transmit buffer in idle
state. The transmit line output changes at the falling edge of the transmit clock pulse as shown in
figures 5.14 (a) and (b). This example uses an 8-bit character, one stop bit, with parity.
A stop bit length of 1, 1.5, or 2 can be specified in 1/16, 1/32, or 1/64 clock mode. In 1/1 clock
mode, only a stop bit length of 1 or 2 is available. Even if 1.5 is specified in this mode, 1 or 2 stop
bits will be used.
Rev. 0, 07/98, page 177 of 453