HD64570 Datasheet, PDF (160/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

3. If enabled, an interrupt request is generated when the residual bit data is ready to be read.
However, in bit synchronous mode, the residual bit interrupt must be disabled because receive
status is usually read from the frame status register (FST).
Abort end frame reception operation: An abort end frame reception operation is shown in
figure 5.4. Abort end frame data is transferred from the receive shift register to the receive buffer,
and the abort end frame status is set in the status FIFO.
Status
Receive buffer FIFO
Empty
Data 1 (8)
Data 2 (8)
Receive buffer
MSB
LSB
Status
FIFO
Data 1 (8)
Data 2 (8)
Data 3 (6)
EOM = 1
ABT = 1
Abort (8)
Receive shift register
Data 5 (8) Data 4 (8)
Data 3 (6)
( ): Bit count
Figure 5.4 Abort End Frame Reception Operation (CRCCC = 1)
1. Part of the aborted data (data 3 in figure 5.4) is transferred from the receive shift register to the
receive buffer. (Data 4 and 5 in figure 5.4 are not transferred to the receive buffer.) At this time,
the bits other than this data are undefined. However, during abort frame reception in bit
synchronous mode, if a zero is inserted in the character immediately before the abort frame, the
preceding 17 bits of data will be discarded. As a result, the three bytes of data before the abort
frame are not received correctly.
2. The EOM and ABT bits of the status FIFO are set to 1.
3. If enabled, an interrupt request is generated when the last data in the frame is ready to be read.
However, in bit synchronous mode, the abort end frame interrupt must be disabled because receive
status is usually read from the frame status register (FST).
Rev. 0, 07/98, page 144 of 453