HD64570 Datasheet, PDF (229/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

ADPLL automatically compensates it to within ±1 operating clock cycle until the clock phase and
receive data phase are synchronized.
ADPLL specifications are shown in table 5.16. The transmission codes supported by the ADPLL
are summarized in figure 1.8.
Table 5.16 ADPLL Specifications
No. Item
Mode
Specification
Remarks
1 Maximum
All
operating clock
frequency
17.6 MHz
2 Maximum bit Operating
rate
mode
× 8 2.2 Mbps
× 16 1.1 Mbps
× 32 0.5 Mbps
3 Maximum
Code type NRZ
number of level
transitions
necessary for
synchronization
×8 4
× 16 8
× 32 16
FM Normal × 8 4
mode
× 16 8
× 32 16
Search
1
mode
Sampling
ratio must
also be set
4 Receive
data noise
suppression
Noise suppression
Operating
mode
On Undefined Off
× 8 x<1/8
1/8≤x<2/8 2/8≤x
× 16 x<2/16 2/16≤x<3/16 3/16≤x
× 32 x<4/32 4/32≤x<5/32 5/32≤x
Rev. 0, 07/98, page 213 of 453