HD64570 Datasheet, PDF (309/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 6.9 shows another example of MSCI-to-memory multi-frame transfer using four descriptors
and four buffers. In this example, to rewrite a buffer, the received data stored in the buffer is
moved to another area during reception operations, and EDA is updated. Steps 1 to 7 are the same
as those in table 6.8. Since the DMAC remains enabled after one frame has been transferred in
multi-frame transfer mode, some frame end interrupts (DMIB) might remain unprocessed. The
number of unprocessed interrupts is stored in the frame end interrupt counter (FCT). When the
FCT value is 1111 and frame transfer continues, a counter overflow error occurs, and the DMAC
terminates data transfer after transmitting the current frame. The FCT value is then reset to 0000,
and DMIA interrupt is generated (if enabled). For details, see sections 6.2.8, DMA Mode Register
(DMR), and 6.2.9, Frame End Interrupt Counter (FCT).
Table 6.9 MSCI-to-Memory Chained-Block Multi-Frame Transfer Mode (part of a buffer
released during reception operation )
DMAC
Step Operation
MPU
CDA EDA DE Bit
Operation Value Value Value Note
1
—
A₁ ‡ CDA A₁
A₀
1
A₀ ‡ EDA
1 ‡ DE bit
Specifies the buffer where the
receive data is to be written using
the CDA (figure 6.21)
2
Writes data to —
buffer 1
A₁
A₀
1
3
A₂ ‡ CDA
A₁ ‡ EDA
A₂
A₁
1
Writes A₁ to EDA to reserve the
maximum buffer size
4
Writes data to —
buffer 2
A₂
A₁
1
5
A₃ ‡ CDA
—
6
Writes data to —
buffer 3
A₃
A₁
1
A₃
A₁
1
7
A₀ ‡ CDA
—
A₀
A₁
1
8
—
Transfers A₀
A₁
1
data from
buffers 1 and
2 to another
area
After transferring receive data to
another area, the MPU rewrites
EDA to release the buffer
(figure 6.21)
9
—
A₃ ‡ EDA
A₀
A₃
1
10 Writes data to —
buffer 0
A₀
A₃
1
A_n: Start address of each descriptor
CDA: Current descriptor address register
EDA: Error descriptor address register
DE bit: Bit 1 of the DMA status register (DSR)
Rev. 0, 07/98, page 293 of 453