HD64570 Datasheet, PDF (440/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Address
Register
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
MSCI (Channel 1)
MSCI Synchronous/
53H 52H
Address Register 0
Channel 1: SA1 Channel 1
7
6
5
4
3
2
1
0
Async
————————
Byte sync
SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10
Bit sync HDLC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
1
1
1
1
1
1
1
1
MSCI Idle Pattern Register 54H
Channel 1: IDL Channel 1
55H
SYN pattern for transmission/address field check
• Byte synchronous mode
Mono-sync
Bi-sync
External-sync
SYN pattern for transmission
SYN pattern for transmission and reception (bit15–bit8)
SYN pattern for transmission
• Bit synchronous mode
No address field checked
HDLC ^{Single address 1}
mode _{Single address 2}
Dual address
Not used
Not used
Bit15–bit8 of the secondary station address
Bit15–bit8 of the secondary station address
7
Async
—
Byte sync
IDL7
Bit sync HDLC
Read/Write R/W
Initial value
1
6
—
IDL6
R/W
1
5
—
IDL5
R/W
1
4
—
IDL4
R/W
1
3
—
IDL3
R/W
1
2
—
IDL2
R/W
1
1
—
IDL1
R/W
1
0
—
IDL0
R/W
1
MSCI Time Constant
Register Channel 1:
TMC Channel 1
55H 54H
Idle pattern
7
6
5
4
3
2
1
0
Async
TMC7 TMC6 TMC5 TMC4 TMC3 TMC2 TMC1 TMC0
Byte sync
Bit sync HDLC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
0
0
0
0
0
0
0
1
Value loaded into the reload timer (1–256)
Rev. 0, 07/98, page 424 of 453