HD64570 Datasheet, PDF (372/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.17 CPU Mode 1 Slave Mode Bus Timing
(V_CC = 5 V ± 5%, V_SS = 0 V, Ta = 0 to +70°C unless otherwise specified)
Item
Symbol Min Typ Max
Address set-up time
t _ADS
15


Address hold time
t _ADH
0


CS set-up time
t _CSS
15


CS hold time
t _CSH
0


RD active set-up time
t _RDS1
15


RD inactive set-up time
t _RDS2
10


RD inactive hold time
t _RDH1
10


RD active hold time
t _RDH2
0


WR active set-up time
t _WRS1
15


WR inactive set-up time
t _WRS2
10


WR inactive hold time
t _WRH1
10


WR active hold time
t _WRH2
0


WAIT active delay time
t _WTD1


50
WAIT inactive delay time
t _WTD2


55
Read data active delay time
t _DBD1


60
Read data hold time
t _DBD2
6


Read data floating delay time
t _DBZ


60
Write data set-up time
t _DBS
15


Write data hold time
t _DBH
20


Note: The CLK timing is the same in this mode and DMA mode.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing
Figure 10.2
Rev. 0, 07/98, page 356 of 453