HD64570 Datasheet, PDF (327/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

7.3.2 Output Timing
Figure 7.3 shows the timer output change timing. When the timer up-counter (TCNT) and the
timer constant register (TCONR) values match and TCNT is subsequently initialized to 0000H,
the CMF bit of the timer control/status register (TCSR) is set to 1, one φ clock cycle later.
TCNT TCNT = TCONR – 1
φ
TCNT = TCONR
1φ
TCNT = 0000H
CMF
φ: Internal clock
CMF bit set (TCNT = 0000H)
Figure 7.3 Timer Output Timing
7.4 Interrupt
When the timer up-counter (TCNT) and the timer constant register (TCONR) values match, the
CMF bit of the timer control/status register (TCSR) is set to 1. Here, an interrupt is generated, if
enabled. (Interrupts initiated by the CMF bit are enabled or disabled by the ECMI bit of TCSR.)
Figure 7.4 shows interrupt timing.
Rev. 0, 07/98, page 311 of 453