HD64570 Datasheet, PDF (214/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Flag
8 bits
A₁
A₂
8 bits 0 or 8 bits
C, I
8 bits x N (N ≥1)
FCS
16 bits
Flag
8 bits
Part to be sent to the receive buffer
(CRCCC = 1)
(CRCCC = 0)
Note: Zeros are inserted to or deleted from the A₁, A ₂, C, I, and FCS fields.
Figure 5.26 Message Format for Bit Synchronous Mode
Transmission Operation: Figure 5.27 is the state transition diagram for transmission in bit
synchronous HDLC mode.
• TX disable state
The transmitter is placed in TX disable state by a hardware reset, a channel reset, or a TX reset
command. In this state, the TXD line is high (mark), and the TXRDY bit of status register 0
(ST0) is cleared.
• Idle state
A transmit enable command sets the transmitter in idle state from TX disable state. In idle
state, the transmitter behaves according to the value of the IDLC bit of the control register
(CTL): repeatedly transmits high (mark) signals when IDLC is 0 or transmits the contents of
the idle pattern register (IDL) when IDLC is 1, via the TXD line. When transmit data is
written, the transmitter enters opening flag transmit state.
• Opening flag transmit state
The transmitter transmits one flag and enters character transmit state.
• Character transmit state
The transmitter sequentially transmits data from the transmit buffer.
• FCS transmit state
The transmitter transmits FCS (CRC) data and enters the next state.
• Closing flag transmit state
The transmitter transmits one flag and enters the next state. (When frames are sent in
succession, they are automatically delimited by at least one closing flag and one opening flag.)
• Abort transmit state
The transmitter transmits abort pattern 11111111 and enters the next state.
Rev. 0, 07/98, page 198 of 453