HD64570 Datasheet, PDF (100/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

7
6
5
4
3
2
1
0
Bit name IMVR7 IMVR6 — — — — — —
Read/Write R/W R/W — — — — — —
Initial value
0
0
0
0
0
0
0
0
Hardware-generated code
Modified vector address
Note: The codes generated for each interrupt source are listed in table 4.2.
Bits 7 and 6 are cleared to 0 by a reset. Bits 5 to 0 always read 0. When writing to IMVR, write 0
in bits 5 to 0.
4.2.3 Interrupt Control Register (ITCR)
The interrupt control register controls the priority order of interrupt sources, and selects the type of
acknowledge cycle and vector output.
Bit name
7
6
5
4
3
2
1
0
IPC IAK1 IAK0 VOS — — — —
Read/Write R/W R/W R/W R/W — — — —
Initial value
0
0
0
0
0
0
0
0
Acknowledge cycle
Interrupt priority 00: Non-acknowledge cycle Vector output
0: MSCI > DMAC 01: Single acknowledge cycle 0: Interrupt vector register
1: DMAC > MSCI 10: Double acknowledge cycle 1: Interrupt modified vector
11: Reserved
Note: Bit 3–bit 0 are reserved. These bits always read 0 and must be set to 0.
Rev. 0, 07/98, page 84 of 453