HD64570 Datasheet, PDF (338/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Wait Control Register M (WCRM): Specifies the number of wait states to be inserted in a
memory cycle when the PAM area is accessed.
Bit name
Read/Write
Initial value
7
6
5
4
3
2
1
0
—
— — — — PAMW2 PAMW1 PAMW0
— — — — — R/W R/W R/W
0
0
0
0
0
1
1
1
PAM area wait
Note: Bit 7 to bit 3 are reserved. These bits always read 0 and must be set to 0.
Bits 7−3: Reserved. These bits always read 0 and must be set to 0.
Bits 2−0 (PAMW2−PAMW0: PAM Area Wait): The function of these bits are described
below.
PAMW2, PAMW1, PAMW0 = 0, 0, 0: Number of wait states = 0
PAMW2, PAMW1, PAMW0 = 0, 0, 1: Number of wait states = 1
PAMW2, PAMW1, PAMW0 = 0, 1, 0: Number of wait states = 2
PAMW2, PAMW1, PAMW0 = 0, 1, 1: Number of wait states = 3
PAMW2, PAMW1, PAMW0 = 1, 0, 0: Number of wait states = 4
PAMW2, PAMW1, PAMW0 = 1, 0, 1: Number of wait states = 5
PAMW2, PAMW1, PAMW0 = 1, 1, 0: Number of wait states = 6
PAMW2, PAMW1, PAMW0 = 1, 1, 1: Number of wait states = 7
Note that PAMW2, PAMW1, and PAMW0 are initialized to (1, 1, 1) at reset.
Rev. 0, 07/98, page 322 of 453