HD64570 Datasheet, PDF (221/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Abort Transmission and Reception: During transmission, the MSCI enables abort transmission
when an abort transmit command is issued. If abort transmission is enabled using the UDRNC bit
of CTL (UDRNC = 0), the MSCI transmitter automatically enters abort transmit state when an
underrun occurs.
This state causes the transmitter to transmit an abort pattern (eight 1s) to clear the transmit buffer.
Thus, the contents of the transmit shift register and transmit buffer are lost. After transmitting the
abort pattern, the MSCI enters idle state.
During reception, the MSCI assumes 01111111 (0 followed by seven 1s) as an abort. On
detecting an abort, the receiver enters flag wait state, generating an interrupt request (if enabled).
If the receiver is in character receive state when the abort is detected, it performs the following
additional operation:
When the CRCCC bit of MD0 is 0, data up to the position preceding 01111111 is sent to the
receive buffer. When the CRCCC bit is 1, data up to the character being assembled at detection is
sent to the receive buffer, and 16 bits of data preceding 01111111 are truncated. (This operation is
the same as for receive frame end on flag detection, except that the ABT bit of ST2 is set to 1.)
Rev. 0, 07/98, page 205 of 453