HD64570 Datasheet, PDF (83/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

In this sequence, after driving BUSREQ active, the SCA samples the BUSACK input from the
master MPU and the BUSY input from the other bus master at each rising edge of CLK. When the
SCA detects BUSACK low and BUSY high, it acquires control of the bus. Having acquired
control of the bus, the SCA drives BUSY (output) low at the next rising edge of CLK and begins a
DMA cycle at the next rising edge of CLK.
If the master MPU drives BUSACK high while the SCA is still requesting control of the bus, the
SCA temporarily releases control of the bus after executing the DMA cycle that began before the
rising edge of CLK at which the SCA sampled BUSACK high. Here, the SCA drives BUSY
(input) high, which indicates the end of the DMA cycles. The specific end timing of DMA cycles
varies depending on the BUSACK input timing and the number of inserted wait states.
Rev. 0, 07/98, page 67 of 453