HD64570 Datasheet, PDF (173/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

5.2.17 MSCI Frame Interrupt Enable Register (FIE)
The frame interrupt enable register (FIE) enables or disables interrupt requests when the EOMF bit
of the frame status register (FST) is set to 1.
Async
7
6
5
4
3
2
1
0
—* —* —* —* —* —* —* —*
Byte sync
Bit sync HDLC EOMFE
Read/Write R/W — — — — — — —
Initial value
0
0
0
0
0
0
0
0
EOMF interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
Note: The bits marked with * are reserved. These bits always read 0 and must
be set to 0.
Bit 7 (EOMFE; EOMF Interrupt Enable): The function of this bit is described below.
• Asynchronous/Byte synchronous mode
Reserved. This bit always reads 0 and must be set to 0.
• Bit synchronous mode
EOMFE = 0: Disables an interrupt set by the EOMF bit of FST
EOMFE = 1: Enables an interrupt set by the EOMF bit of FST; the RXINT bit of ST0 is set to
1 when the EOMF and EOMFE bits are both 1
Bits 6−0: Reserved. These bits always read 0 and must be set to 0.
Rev. 0, 07/98, page 157 of 453