HD64570 Datasheet, PDF (323/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit name
Read/Write
Initial value
7
6
5
4
3
2
1
0
—^*1 —^*1 —^*1 —^*1 —^*1 ECKS2 ECKS1 ECKS0
— — — — — R/W R/W R/W
0
0
0
0
0
0
0
0
Notes: 1. Bit 7 to bit 3 are reserved.
These bits always read 0 and must be set to 0.
2. BC (base clock) is obtained by dividing system
clock φ by eight.
Expand clock input select
000: BC^*2
001: BC^*2/2
010: BC^*2/4
011: BC^*2/8
100: BC^*2/16
101: BC^*2/32
110: BC^*2/64
111: BC^*2/128
Bits 7−3: Reserved. These bits always read 0 and must be set to 0.
Bits 2−0 (ECKS2−ECKS0: Expand Clock Input Select): Selects the TCNT clock as shown
below. These bits are cleared at reset.
ECKS2, ECKS1, ECKS0 = 0, 0, 0: TCNT clock rate = BC
ECKS2, ECKS1, ECKS0 = 0, 0, 1: TCNT clock rate = BC/2
ECKS2, ECKS1, ECKS0 = 0, 1, 0: TCNT clock rate = BC/4
ECKS2, ECKS1, ECKS0 = 0, 1, 1: TCNT clock rate = BC/8
ECKS2, ECKS1, ECKS0 = 1, 0, 0: TCNT clock rate = BC/16
ECKS2, ECKS1, ECKS0 = 1, 0, 1: TCNT clock rate = BC/32
ECKS2, ECKS1, ECKS0 = 1, 1, 0: TCNT clock rate = BC/64
ECKS2, ECKS1, ECKS0 = 1, 1, 1: TCNT clock rate = BC/128
Rev. 0, 07/98, page 307 of 453