HD64570 Datasheet, PDF (417/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Register
Interrupt Control
Interrupt Enable
Register 2 (IER2)
Address
CPU CPU
Mode Mode
0, 1 2, 3 Remarks
16H 17H
7
6
5
4
3
2
Bit name T3IRQET2IRQET1IRQET0IRQE — —
1
0
——
Read/Write R/W R/W R/W R/W — — — —
Initial value
0
0
0
0
0
0
0
0
Timer channel 3
interrupt request enable
0: Disabled
1: Enabled
Timer channel 0
interrupt request enable
0: Disabled
1: Enabled
Not used
17H
Interrupt Control Register 18H
(ITCR)
16H
19H
Timer channel 2
interrupt request enable
0: Disabled
1: Enabled
Timer channel 1
interrupt request enable
0: Disabled
1: Enabled
Bit name
7
6
5
4
3
2
1
0
IPC IAK1 IAK0 VOS — — — —
Read/Write R/W R/W R/W R/W — — — —
Initial value
0
0
0
0
0
0
0
0
Acknowledge cycle
Interrupt priority 00: Non-acknowledge cycle Vector output
0: MSCI > DMAC 01: Single acknowledge cycle 0: Interrupt vector register
1: DMAC > MSCI 10: Double acknowledge cycle 1: Interrupt modified vector
11: Reserved
Not used
19H 18H
Rev. 0, 07/98, page 401 of 453