HD64570 Datasheet, PDF (245/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit Rate
(bps)
f_CLK (MHz)
3.072
4
TMC BR CM Deviation (%) TMC BR CM Deviation (%)
38400 5
0
1/16 0.00




19200 5
0
1/32 0.00
13
0
1/16 0.16
9600 5
0
1/64 0.00
13
0
1/32 0.16
4800 5
1
1/64 0.00
13
0
1/64 0.16
2400 5
2
1/64 0.00
13
1
1/64 0.16
1200 5
3
1/64 0.00
13
2
1/64 0.16
600
5
4
1/64 0.00
13
3
1/64 0.16
300
5
5
1/64 0.00
13
4
1/64 0.16
150
5
6
1/64 0.00
13
5
1/64 0.16
110
109 2
1/64 0.08
71
3
1/64 0.03
TMC:
BR:
CM:
Value of the TMC7−TMC0 bits of TMC
Value of the TXBR3−TXBR0 bits of TXS or the RXBR3−RXBR0 bits of RXS
Value of the BRATE1−BRATE0 bits of MD1 (clock mode in asynchronous mode (bit
rate/clock frequency))
Table 5.21 Register Set Values and Bit Rates in Asynchronous Mode (cont)
Bit Rate
(bps)
TMC BR
38400 

19200 15
0
9600 15
0
4800 15
0
2400 15
1
1200 15
2
600
15
3
300
15
4
150
15
5
110
41
4
4.608
f_CLK (MHz)
CM Deviation (%) TMC BR


1
1
1/16 0.00
1
2
1/32 0.00
1
3
1/64 0.00
1
4
1/64 0.00
1
5
1/64 0.00
1
6
1/64 0.00
1
7
1/64 0.00
1
8
1/64 0.00
1
9
1/64 −0.22
175 2
4.9152
CM Deviation (%)
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 0.00
1/64 −0.25
Rev. 0, 07/98, page 229 of 453