HD64570 Datasheet, PDF(239/469 Page) Hitachi Semiconductor – Serial Communications Adaptor

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HD64570 Datasheet, PDF (239/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

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Notes on Clock Extraction: NRZ-type codes differ from FM-type codes in that the data does not

include a clock component. Accordingly, when the ADPLL is used to receive NRZ-type encoded

data by extracting the clock from the data, receive data including a level transition on the RXD

line must be supplied periodically to ensure that the ADPLL does not lose synchronization.

Table 5.18 gives precautions necessary for each type of encoding in each protocol mode.

Table 5.18 Notes on Clock Extraction

Class

Code Protocol Mode Description

NRZ-type NRZ,

NRZI

Byte

synchronous

mode

Ensure that t0 < tADPLL (NRZ only) and t1 < tADPLL. Before

transmitting SYN characters, transmit an appropriate

synchronization pattern in the idle state to synchronize the

ADPLL. (See note 1.)

Bit

synchronous

mode

Ensure that t0 < tADPLL (NRZ only) and that (6 clock cycles)

< tADPLL (because a flag has six consecutive 1s). Before

transmitting an opening flag, transmit an appropriate

synchronization pattern in the idle state to synchronize the

ADPLL. (See note 1.)

FM-type

FM0, Byte

FM1, synchronous

Manch- mode, bit

ester synchronous

mode

In the idle state, have the receiver receive a synchronization

pattern, and issue the enter search mode command to

synchronize the ADPLL. (See note 2.)

t0:

t1:

t : ADPLL

Maximum interval containing consecutive 0 data

Maximum interval containing consecutive 1 data

Minimum interval in which ADPLL synchronization can be lost by receiving consecutive

data at the same level.

Notes: 1. See table 5.16 for the number of transition points needed in the synchronization pattern.

2. For further information about ADPLL synchronization with an FM-type code, see

section 5.4.5, "Notes on Use."

ADPLL Receive Margin: Table 5.19 indicates the theoretical ADPLL receive margin

(the tolerable bit distortion and bit rate distortion).

As shown in figure 5.42, t0 is the width of one bit in the ideal waveform, and it is the width in the

actual waveform. T0 and T are the ideal and actual time occupied by an arbitrary number of bits.

Compared with the Ã 8 operating mode, the Ã 32 operating mode samples each bit of input on the

RXD line more often, so the bit margin is higher, but less phase compensation is applied each time

by the ADPLL, so the bit rate margin is lower.

Rev. 0, 07/98, page 223 of 453

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