HD64570 Datasheet, PDF (365/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Table 10.9 CPU Mode 2, 3 Master Mode Bus Timing
(V_CC = 5 V ± 10%, V_SS = 0 V, Ta = −20 to +75°C unless otherwise specified)
Item
Clock cycle time
Symbol Min Typ Max Unit
t _CYC
100 
2000 ns
Clock high-level pulse width
Clock low-level pulse width
Clock fall time
Clock rise time
Address delay time 1
Set-up time from AS
AS delay time
HDS, LDS delay time 1
Hold time from AS 1
Hold time from AS 2
HDS, LDS delay time 3
Read data set-up time
Read data hold time
WAIT set-up time
WAIT hold time
HDS, LDS delay time 2
HDS, LDS low-level pulse width
Write data delay time
Write data set-up time
Write data hold time
Write data floating delay time
AS high-level pulse width
Read data strobe hold time
t _CH
t _CL
t _cf
t _cr
t _AD1
t _ASS
t _ASD
t _DSD1
t _ASH1
t _ASH2
t _DSD3
t _RDS
t _RDH
t _WTS
t _WTH
t _DSD2
t _DSW
t _WDD
t _WDS
t _WDH
t _WDZ
t _ASW1
t _RDHX
40


ns
40


ns


10
ns


10
ns


60
ns
15


ns


50
ns


50
ns
10


ns
10


ns


55
ns
25


ns
20


ns
30


ns
30


ns


50
ns
110 

ns


60
ns
15


ns
10


ns


60
ns
70


ns
0


ns
Timing
Figure 10.8,
figure 10.9
Rev. 0, 07/98, page 349 of 453