HD64570 Datasheet, PDF (262/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

6.2.5 Receive Buffer Length Register (BFL: BFLL, BFLH)
One set of two 8-bit subregisters, serving as the receive buffer length register (BFL: BFLL,
BFLH), is provided for each of channels 0 and 2 (figure 6.5).
Single-Block Transfer Mode: In single-block transfer mode, these subregisters are not used.
Their contents have no effect on operation.
Chained-Block Transfer Mode: In chained-block transfer mode, these subregisters serve as the
receive buffer length register (BFL: BFLL, BFLH). This register specifies the buffer length in
memory in byte units only in MSCI-to-memory chained-block transfer mode.
This register must be set in DMA initial state. In chained-block transfer mode, the receive buffer
length register (BFL) must not be 1 in CPU modes 0, 2, and 3, since data may be transferred in
word units.
The above restrictions do not apply to CPU mode 1 or transmission operation.
After reset, the value of this register is undefined.
H
L
15
87
0
Single-block transfer
mode
Chained-
block trans-
fer mode
Memory to
MSCI
MSCI to
memory
Not used
Not used
BFLH
Not used
Not used
BFLL
Figure 6.5 Receive Buffer Length Register
6.2.6 Byte Count Register (BCR: BCRL, BCRH)
One set of two 8-bit subregisters, serving as the byte count register (BCR: BCRL, BCRH), is
provided for each of channels 0, 1, 2, and 3 (figure 6.6).
Single-Block Transfer Mode: In single-block transfer mode, BCR specifies the number of bytes
to be transferred (up to 64 Kbytes). The BCR value is decremented by 1 each time one byte of
data is transferred by the DMAC or decremented by 2 each time one word of data is transferred.
The transfer operation terminates when the value becomes 0000H. If 0000H is set as the initial
value, 64 Kbytes of data will be transferred.
Rev. 0, 07/98, page 246 of 453