HD64570 Datasheet, PDF (302/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

HD64570
CPB (8 bits)
EDA (16 bits)
CDA (16 bits)
BAR (24 bits)
BCR (16 bits)
BFL (16 bits)
High-order 8 bits of the
descriptor address
System memory
Descriptor
Buffer
Start address of the
write overflow descriptor
(low-order 16 bits)
Start address of the
descriptor being written
(low-order 16 bits)
Memory address of
the data being written
Byte count of the data
remaining in the buffer
being written
Current write position
Receive buffer length
(byte count)
CPB: Chain pointer base
EDA: Error descriptor address register
CDA: Current descriptor address register
BAR: Buffer address register
BCR: Byte count register
BFL: Receive buffer length
: Empty buffer
: Receive data
Figure 6.18 MSCI-to-Memory Chained-Block Transfer
The operation flow in MSCI-to-memory chained-block transfer mode is shown in figure 6.19. As
shown in the figure, the DMAC transfers data from the MSCI receiver to the buffer corresponding
to the descriptor specified by CPB and CDA. At this time, the DMAC writes the 24-bit memory
address of the buffer currently being written to the buffer address register (BAR) and the number
of bytes remaining unwritten in the buffer to the byte count register (BCR). When data transfer
starts, the DMAC writes the BP value of the corresponding descriptor to BAR and the BFL value
to BCR.
The BAR value is incremented by 1 or 2 each time one byte or one word of data is transferred,
respectively. Similarly, the BCR value is decremented by 1 or 2 each time one byte or one word
of data is transferred, respectively. When the BCR value reaches 0000H, the DMAC terminates
data transfer, writes the receive data length to the descriptor, and updates the CDA value to
indicate the start address of the next descriptor (buffer switching). The DMAC, at that time,
Rev. 0, 07/98, page 286 of 453