HD64570 Datasheet, PDF (87/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

MPU
BHE D₁₅ to D₈ D₇ to D ₀ A₀
MPU
HDS D₁₅ to D₈ D₇ to D ₀ LDS
E D₁₅ to D₈
Odd-address
memory bank
D₇ to D ₀ E
Even-address
memory bank
E D₁₅ to D₈
Even-address
memory bank
D₇ to D ₀ E
Odd-address
memory bank
Figure 3.8 Data Bus Mapping onto Memory Banks in CPU Modes 0, 2, and 3
3.4.2 Slave Mode Bus Cycle
In slave mode, data moves from the SCA to MPU in a read cycle, and from MPU to the SCA in a
write cycle. The address and bus interface signals are input signals, except for WAIT, which is an
output signal.
CPU Mode 0: The SCA latches BHE and the address on lines A0 to A7 when CS is driven active
low. CS must remain low throughout the bus cycle. After the bus cycle ends, CS may be either
high or low. CS may also be low before the beginning of the bus cycle. Figure 3.9 shows the slave
mode bus timing sequence in CPU mode 0.
• Read cycle
If RD is low (active) at the falling clock edge between the T₁ and T₂ states, the SCA outputs
the contents of the register specified by the address on the data bus on the rising clock edge in
the T₃ state. RD must remain low until the beginning of the T₄ state. When RD goes high
(inactive), the cycle ends: the SCA then drives the WAIT output active high and lets the data
bus float. The read cycle can be extended by delaying the high transition of RD.
• Write cycle
If WR is low (active) at the falling clock edge between the T₁ and T₂ states, the SCA latches
the data on the data bus on the rising clock edge in the T₃ state, and stores the data in the
register specified by the address. WR must remain low until the rising clock edge in the T₄
state. When WR goes high (inactive), the cycle ends: the SCA then drives the WAIT output
active high.
When successive slave mode bus cycles or interrupt acknowledge cycles occur in CPU mode
0, at least one T_i state (idle state) must be inserted between cycles. No T_i state is necessary
when the next cycle is not a slave mode bus cycle or an interrupt acknowledge cycle.
Rev. 0, 07/98, page 71 of 453