HD64570 Datasheet, PDF (332/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Bit name
Read/Write
Initial value
7
6
5
4
3
2
1
0
PB07 PB06 PB05 PB04 PB03 PB02 PB01 PB00
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
PAL/PAM boundary address (high-order 8 bits)
This register can specify only the high-order eight bits (A₂₃−A₁₆) of the boundary address; the
remaining low-order 16 bits (A₁₅−A₀) are fixed to 0000H. Thus, each area is specified in
64-Kbyte units.
When PABR0 is set to 00H, the boundary is at the top of the memory space.
Physical Address Boundary Register 1 (PABR1): Specifies the high-order eight bits of the
boundary address between PAM and the physical address high area (PAH). This address is the
lower limit address of PAH.
Bit name
Read/Write
Initial value
7
6
5
4
3
2
1
0
PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10
R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
PAM/PAH boundary address (high-order 8 bits)
This register can specify only the high-order eight bits (A₂₃−A₁₆) of the boundary address; the
remaining low-order 16 bits (A₁₅−A₀) are fixed to 0000H. Thus, each area is specified in
64-Kbyte units.
When PABR1 is set to 00H, the boundary is at the top of the memory space.
Boundary Address Setting Examples: The memory space is usually divided into three areas:
PAL, PAM, and PAH, as shown in figure 8.1. The boundary between PAL and PAM (the high-
order eight bits of the lower limit address of PAM) is specified by PABR0, and that between PAM
and PAH (the high-order eight bits of the lower limit address of PAH) is specified by PABR1, in
64-Kbyte units. In the figure, PABR0 and PABR1 are set to 01H and 40H, respectively. In this
case, each memory area is specified as follows:
Rev. 0, 07/98, page 316 of 453