HD64570 Datasheet, PDF (158/469 Pages) Hitachi Semiconductor – Serial Communications Adaptor

Reserved. This bit always reads 0 and can be set to 0 or 1.
• Bit synchronous mode
The ABT bit indicates whether or not an abort end frame has been detected.
This bit is set to 1 by the character preceding the abort sequence when the receive frame ends
with an abort. When this bit is set to 1, the EOM bit is also set to 1. See Abort End Frame
Reception Operation below.
ABT = 0: Indicates that no abort end frame has been detected
ABT = 1: Indicates that an abort end frame has been detected
Bit 4 (FRME/RBIT: Framing Error/Residual Bit Frame): Indicates a framing error detection
in asynchronous mode, and residual bit frame detection in bit synchronous mode. This bit is
cleared when 1 is written to this bit position.
• Asynchronous mode
FRME = 0: Indicates that no framing error has occurred
FRME = 1: Indicates that a framing error has occurred
Once set to 1, this bit is not cleared until the receiver is reset or 1 is written to this bit position.
• Byte synchronous mode
Reserved. This bit always reads 0 and can be set to 0 or 1.
• Bit synchronous mode
RBIT = 0: Indicates that no residual bit frame has been detected
RBIT = 1: Indicates that a residual bit frame has been detected
When the CRCCC bit of MD0 is 1, this bit is set to 1 by the residual bit of the last character in
the receive frame I field. When the CRCCC bit is 0, the RBIT bit is set to 1 by the residual bit
of the last character of FCS.
When the RBIT bit is set to 1, the EOM bit is also set to 1. See Residual Bit Frame Reception
Operation below.
Bit 3 (OVRN: Overrun Error): Indicates whether or not an overrun has occurred. This bit is
cleared when 1 is written to this bit position. In asynchronous and byte synchronous modes, this
bit is cleared when 1 is written to this bit position, or the receiver is reset. In bit synchronous
mode, all bits of this register are also reset when the status data is loaded into the frame status
register (FST).
• Asynchronous/Byte synchronous/Bit synchronous modes
OVRN = 0: Indicates that no overrun error has occurred
OVRN = 1: Indicates that an overrun error has occurred
Bit 2 (CRCE: CRC Error): Indicates whether or not a CRC error has occurred in byte or bit
synchronous mode.
• Asynchronous mode
Rev. 0, 07/98, page 142 of 453